/* 
 * --------------------
 * Company					: LUOYANG GINGKO TECHNOLOGY CO.,LTD.
 * BBS						: http://www.eeschool.org
 * --------------------
 * Project Name			: USART
 * Module Name				: USART
 * Description				: The codes of "USART"
 * --------------------
 * Tool Versions			: Quartus II 13.1
 * Target Device			: Cyclone IV E  EP4CE10F17C8
 * --------------------
 * Engineer					: Xiaorenwu
 * Revision					: V0.0
 * Created Date			: 2016-04-06
 * --------------------
 * Engineer					:
 * Revision					:
 * Modified Date			:
 * --------------------
 * 
 * --------------------
 */

//--------------------Timescale------------------------------//
`timescale 1 ns / 1 ps
//--------------------Module_USART_Top------------------//
	module   USART_Top (	
						input CLK_25M,
						input RX,
						output TX,
						output FPGA_LEDR,FPGA_LEDG,FPGA_LEDB,
						output A,_A,B,_B
						);	
						
	RST_Ctrl		U1(
						.CLK_25M(CLK_25M),
						.rst_n(rst_n)
						);

	BPS_Ctrl		U2(
						.CLK_25M(CLK_25M),
						.rst_n(rst_n),
						.BPS_CLK(BPS_CLK)
						);

	TXD_RXD_Ctrl	U3(
						.rst_n(rst_n),
						.BPS_CLK(BPS_CLK),
						.RX(RX),
						.FPGA_LEDR(FPGA_LEDR),
						.FPGA_LEDG(FPGA_LEDG),
						.FPGA_LEDB(FPGA_LEDB),
						.TX(TX),
						.A(A),
						._A(_A),
						.B(B),
						._B(_B)
						);			
						
endmodule						
						